Robustness against electrostatic discharge (ESD) is a critical reliability issue in advanced CMOS technologies. To prevent circuit damage due to ESD events (which can expose the circuit to kV range voltages), ESD clamp circuits are typically incorporated in supply pad library cells. These circuits use extremely wide devices (100 s of μm) and thus exhibit leakage currents of 10 nA to 10 pA (at 25° C. and 125° C., respectively) despite the use of various low power approaches. Recently, there has been increased interest in ultra-low power wireless sensor node systems with constrained battery sizes and system standby power budgets as low as 10-100 nW. Considering the need for multiple power pads, these systems cannot use existing ESD structures due to their high leakage, thereby compromising their reliability.
To address this challenge, the present disclosure provides three ultra-low leakage ESD circuits that use special biasing structures to reduce subthreshold leakage and gate-induced drain leakage (GIDL) while maintaining ESD protection. In 180 nm silicon test chip results, the proposed clamp circuit demonstrate 10 s of pA (nA) operation at room temperature (125° C.), which is a >100× improvement over prior state of the art.
This section provides background information related to the present disclosure which is not necessarily prior art.